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Ingeniero vlsi Interview Questions

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PathPartner Technology
Xillinx Software Engineer for VLSI was asked...29 August 2016

Difrence between synchronous and asynchronous

2 Answers

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Dint say

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In asynchronous ckt, the output does not depends on clock, it depends on the reset of the device only Less

Dxcorr Design
VLSI ENGINEER was asked...24 April 2018

Stick diagram for 3 input Nand gate.

2 Answers

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I knew the stick diagram. So I was able to answer it.

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I knew

Dxcorr Design
VLSI Design Engineer was asked...7 January 2016

1) Be prepare on basics of logic design---FF,counter,adder,subtractior,Decoder

1 Answers

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Location sir

VLSI Design Or Verification Engineer was asked...29 December 2021

Tell me something about yourself. Why you are choosing to be a VLSI Design or Verification Engineer. You are interested in data science and choosing VLSI, why?

1 Answers

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I answered very well

InSemi Technology Services
VLSI Verification Engineer was asked...14 May 2022

Question based on digital electronics, verilog, edc.

1 Answers

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Just clear the basics concept.

UST
VLSI Design Engineer was asked...12 December 2019

Tell me about yourself

1 Answers

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How do you fix crosstalk ?

HCLTech
VLSI Design Engineer was asked...11 October 2017

5: universal gates

1 Answers

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Nand and nor gates

Analog Devices
VLSI Design Engineer was asked...21 October 2019

Mainly Digital electronics was asked... Flipflops synchronous counter... FSM....

1 Answers

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Refer to a specific book digital integrated circuits be good in thought process

Intel Corporation
VLSI Design Engineer was asked...28 November 2011

discuss about charge sharing

1 Answers

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Charge sharing is one of the main issues in Dynamic logic. Charge stored at the output load is redistributed or shared among capacitance of other transistors which are in evaluation phase.This leads to reduced output level Less

Wipro
VLSI Project Engineer was asked...20 April 2016

function to count the number of ones in system verilog

1 Answers

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$countones

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