Yield enhancement engineer Interview Questions

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Micron Technology
Yield Enhancement Engineer was asked...25 February 2021

1. Leakage mechanisms 2. CMP - advantages and issues 3. Processes impacting Vt and other device parameters 4. Questions on DRAM working principles 5. Questions on yield analysis 6. Basic statistics - p-value, hypothesis testing, mean, median, mode, etc.

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Where do you see yourself in 5 years

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Draw a circuit

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CMOS Basics Operation and some MOSFET related.

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1.Typical Phone interview with 2 Managers who asked about DRAM, NAND basic understanding, did stress on behavioral questions and stressed upon 1 question regarding difficult customer and how will you react to such situation? 2. 2nd Phone interview was taken by Area manager with rapid fire question round with basic material science, which was quiet interesting and tests your basics. 3.Onsite interview consisted of different technical rounds: interestingly the interviewers showed different SEM images and asked to find the defect. 4.Few engineers asked about semiconductor process knowledge as well as CMOS, transistor knowledge.

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What is your career objective in the next 5 years?

1 Answers

Improve my ability and contribute to the firm.

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Draw a NAND or NOR CMOS gate. Which one is this? Why do we draw PMOS on top? What is the benefit of having PMOS connected to Vdd?

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Delay problem: A 10 ns delay is connected to one input of a NAND gate, a 2.5 ns delay inverter is connected to the other. Input is high until 10 ns, then goes high again at 50 ns. What is the behavior of the output?

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Charge Sharing Problem: what are the final Caps and Voltages after the switch is thrown, connecting the capacitors?

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Process Engineering Question: What are two ways to limit or control an etch?

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