I applied through university. I interviewed at Broadcom
Interview
One Telephonic Interview. I had an experience in ASIC Verification. So they only asked about my UVM Background. It was easy and got the offer at once. One can expect basic logic design questions and basics of Verilog
Got a phone call to set up interview. It was a phone Interview. said about the position and later asked about academic project. Questions where about sequence detector, assembly code to alter particular bits, perl and C++. Difference between blocking and non blocking from verilog.
In sequence detector, it was 1101 sequence. After I came up with state diagram ( he said any one mealy or moore) he asked to explain it giving some sequence and asked if my state diagram satisfy for any sequence.
C++ was just concept no coding.
Interview questions [1]
Question 1
There where no unexpected questions. All the questions where moderate.