Got a phone call first. Basic concentration was on testbench experience, work experience, how u develop an tb, uvm/ovm basics, testplaning basics, pci express knowledge, work exp i did very well but they took >30 days to get back. invited for an onsite interview. it lasted for 6 rounds first round: Clock domain crossing issues, how to solve, what to do if it's a bus, design a fsm, divide by 2,3 behavioural codes using shift registers, meta stability, how u solve, how u model it in env 2) CDC, pcs layer, pci express school project, phy layer questions how u implement in behavioural modeling, tb architecting questions, CDC fifo questions, block level model. why 8b/10b encoding in pcie, how signalling is done, ltssm questions 3) SV, basics, verilog basics, delays waveforms, timing, fixes, other stupid questions which didn't make much sense. his answers were very theoretical not a practical applications. 4)same questions from previous rounds. more concentration on how pcie device works, various layers, test planing, tb development, execution related questions, more technica questions 5) lunch. behavioural, my experience in varuos senarios 6)same questions from prev rounds. my environment questions, uvm, sv questions, perl codes, pll questions, phy related questions good interview process. grilled every aspect. but decioson making is insane. i did extremly well but they still didn't get back and i had another offer. team members were very nice