I applied online. The process took 1 week. I interviewed at Qualcomm (Chennai) in Jan 2024
Interview
started with intro and ended with thankyou. they asked digital electronics basics/ physical design flow, sta concepts, some questions from signoff stage. second round was directly they given marker and asked me to solve sta related violation.
4 interviewers.
Basics of physical design /cpu architecture/experience based questions/tcl scripting/timing analysis/block closure /techniques/previous wrk exp/ drc analysis related questions/ tool related questions/ example
Based questions “how would you solve this?” Kind of questions
Interview questions [1]
Question 1
Explain the challenges involved in previous tapeout
Application via Qualcomm careers or referral.
Recruiter may reach out for basic screening:
Your background, tools used (ICC2, PrimeTime, RedHawk, etc.)
Areas of expertise: floorplanning, CTS, routing, STA, DRC, EMIR, etc.
Experience with multi-VDD, ECOs, hierarchical designs, colored flows, etc.
Technical Phone Interviews (1–2 rounds)
Each round typically lasts 45–60 minutes.
Interview questions [1]
Question 1
Walk me through how you approach floorplanning for a block.
How do you handle placement of macros and standard cells around them?
What considerations go into designing a power grid?
How do you handle multi-VDD domains or level shifters?
What are tie-high and tie-low cells and where are they used?
