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      Intel Corporation

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      Soc Design Verification Engineer Interview

      6 May 2016
      Anonymous interview candidate
      Fort Collins, CO
      No offer
      Positive experience
      Average interview

      Application

      I applied online. The process took 1 day. I interviewed at Intel Corporation (Fort Collins, CO) in Mar 2016

      Interview

      The entire interview experience was very good. Had a brief phone round where I was asked questions on computer architecture fundamentals like cache, pipelining. Then onsite I had 5 rounds, 4 technical and 1 behavioral. 1 round was on computer architecture and problem solving where I was asked questions on cache coherency, and one design problem for a 4-way set associative cache. 2nd round was on logic design where I had to design a FSM for a vending machine and few other timing and k-map simplification questions. 3rd round was on validation which was more like a discussion covering a lot of verification concepts starting from assertions, coverage, golden test vectors etc. Then after lunch, I had the behavioral round where the manager mostly went into the details of my resume. Then my 5th round was on software which had lot of psuedo codes and I had to correct them, make some changes and also lot of one line questions covering all oops concepts, data structures etc. Overall, my interview experience was excellent and I was expecting an offer but don't know why they rejected me.

      Interview questions [1]

      Question 1

      Computer Architecture, Logic design, validation, software, behavioral.
      Answer question
      1

      Other Soc Design Verification Engineer interview reviews for Intel Corporation

      Soc Design Verification Engineer Interview

      22 May 2025
      Anonymous employee
      Accepted offer
      Positive experience
      Difficult interview

      Application

      I interviewed at Intel Corporation

      Interview

      There was totally 3 rounds of Interview and process was smooth. Interviewers were clear in their questions.Each round of interview lasted about 1hr 15mins. Feedback was given in time. Overall smooth process

      Interview questions [1]

      Question 1

      Questions about debug of failure
      Answer question

      Soc Design Verification Engineer Interview

      20 Jun 2025
      Anonymous employee
      Vancouver, BC
      Accepted offer
      Positive experience
      Average interview

      Application

      I applied through an employee referral. The process took 4 weeks. I interviewed at Intel Corporation (Vancouver, BC) in Apr 2025

      Interview

      There is one managerial round, two technical rounds with two panel members each, and an hr round. The whole process was 1 month. mainly focus on system verilog assertions, coverage, constraint randomisation.

      Interview questions [1]

      Question 1

      1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
      Answer question

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