I applied in-person. I interviewed at Intel Corporation (Austin, TX) in May 2019
Interview
Applied by sending resume directly to manager .First round was telephonic ,lasted for 40 minutes . Background check in parallel, 5 more technical rounds at onsite.All interviewers were good and understanding.
Interview questions [1]
Question 1
Telephonic:Process and Temp variation for delays,Voltage and TEmperature effect on Metal LAyer,Synthesis flow:Inputs.How do u do floorplanning.?Power types and methods to control,DRC,challenges during placementa nd congestion
Onsite; First ROund:Whole RTL to Netlist flow in detail,Timing correlation,miller effect,virtual routes),Sceond ROund: How do u solve DC and ICC correlation:DC putting lots of buffers-Reasons,How will u solve clock transition if sizing is not posibble(Explain MErging), 3rd Round : TECH DRC Questions :One problem was given :write a script to replace with right optimized via in power plan .4th Round :STA problems,3 equations -waveforms;derate effects,positive and negative edge flops at capturing end.5th ROund: Custom Bus routing (How to do manually for timing critical path),Script to find occurences of via in design by reference name and reduce runtime by not using get_cells twice.
very nice people. given 2 question one on system of the group and one for coding in binary search and recursion. we started by little talking and then a little bit on one of the project and then 2 questions
Interview questions [1]
Question 1
1. given graph and car with light sensor and we want to find the right spot of the dot on the graph. it was binary search classical
I applied online. I interviewed at Intel Corporation (Bengaluru) in May 2026
Interview
Deep whiteboard interview , was asked to draw graphs for non ideal characteristics for cmos design and pvt corners. Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
Interview questions [1]
Question 1
was asked to draw graphs for non ideal characteristics for cmos design and pvt corners.Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
This was the second round lasted about an hour or so. The first round was mostly about my work as I had 3 year experience and I had to walk them through the projects I did etc..,.
Interview questions [1]
Question 1
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.