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      Physical Design Engineer Interview

      18 Jun 2015
      Anonymous interview candidate
      Raleigh, NC
      No offer
      Positive experience
      Average interview

      Application

      I applied online. I interviewed at Qualcomm (Raleigh, NC) in Feb 2015

      Interview

      Was very straight forward. easy rounds. Static Timing Analysis, Timing Closure. Synthesis, Clock Tree Synthesis, Floor planning, Place and Route, RTL and netlist synthesis. Questions based on projects, PERL, Clock Tree Distribution, Power and Ground area, Die area

      Interview questions [1]

      Question 1

      Static Timing Analysis
      1 Answer
      4

      Other Physical Design Engineer interview reviews for Qualcomm

      Physical Design Engineer Interview

      6 Oct 2025
      Anonymous employee
      Accepted offer
      Positive experience
      Difficult interview

      Application

      I interviewed at Qualcomm

      Interview

      4 interviewers. Basics of physical design /cpu architecture/experience based questions/tcl scripting/timing analysis/block closure /techniques/previous wrk exp/ drc analysis related questions/ tool related questions/ example Based questions “how would you solve this?” Kind of questions

      Interview questions [1]

      Question 1

      Explain the challenges involved in previous tapeout
      Answer question

      Physical Design Engineer Interview

      4 Jun 2025
      Anonymous interview candidate
      San Diego, CA
      No offer
      Negative experience
      Difficult interview

      Application

      I interviewed at Qualcomm (San Diego, CA)

      Interview

      Application via Qualcomm careers or referral. Recruiter may reach out for basic screening: Your background, tools used (ICC2, PrimeTime, RedHawk, etc.) Areas of expertise: floorplanning, CTS, routing, STA, DRC, EMIR, etc. Experience with multi-VDD, ECOs, hierarchical designs, colored flows, etc. Technical Phone Interviews (1–2 rounds) Each round typically lasts 45–60 minutes.

      Interview questions [1]

      Question 1

      Walk me through how you approach floorplanning for a block. How do you handle placement of macros and standard cells around them? What considerations go into designing a power grid? How do you handle multi-VDD domains or level shifters? What are tie-high and tie-low cells and where are they used?
      Answer question
      1

      Physical Design Engineer Interview

      23 Apr 2024
      Anonymous interview candidate
      Chennai
      Declined offer
      Positive experience
      Easy interview

      Application

      I applied online. The process took 1 week. I interviewed at Qualcomm (Chennai) in Jan 2024

      Interview

      started with intro and ended with thankyou. they asked digital electronics basics/ physical design flow, sta concepts, some questions from signoff stage. second round was directly they given marker and asked me to solve sta related violation.

      Interview questions [1]

      Question 1

      it was good and interesting
      Answer question

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