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      ASIC Physical Design Engineer Interview

      17 Nov 2017
      Anonymous interview candidate
      Cupertino, CA
      No offer
      Positive experience
      Average interview

      Application

      I applied through a recruiter. The process took 3 weeks. I interviewed at Apple (Cupertino, CA) in Nov 2017

      Interview

      Whole process was average length as far as engagements go. First week, I spoke with HR. Second week, did a phone screen with hiring manager. Third week, was the on site with four interviewers. Two were through video conf.

      Interview questions [1]

      Question 1

      How is uncertainty determined.
      Answer question
      5

      Other ASIC Physical Design Engineer interview reviews for Apple

      ASIC Physical Design Engineer Interview

      26 Feb 2024
      Anonymous interview candidate
      Sunnyvale, CA
      No offer
      Positive experience
      Average interview

      Application

      I applied online. The process took 4 weeks. I interviewed at Apple (Sunnyvale, CA) in Dec 2023

      Interview

      There were two rounds of interview: One screening interview and three interviews with three different members from the team. Interviewed on topics related to VLSI and Digital Electronics. Smooth and to the point interview process.

      Interview questions [1]

      Question 1

      What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
      Answer question