Location:
F10 Singapore. 1 North Coast Drive
Department:
Process & Equipment Engineering

Project Title:
F10 N and W Complementary Metal Oxide Semiconductor Matching and Wafer Edge Exclusion Optimisation

Project Description:
This internship project focuses on yield improvement through advanced process analysis and wafer edge performance optimisation within semiconductor manufacturing. The intern will examine matching behaviour between N and W process flows and evaluate wafer edge exclusion performance to reduce yield losses attributed to edge‑related effects. The project emphasises data‑driven analysis, defectivity characterisation, and inspection metric enhancement to enable sustained manufacturing performance.

Objective of the Project:
The objective is to identify key contributors to process mismatch and wafer edge yield loss, and to develop analytical methodologies that strengthen yield performance and inspection accuracy in a production environment.

Project Scope:
The project involves analysing inline, defect, and inspection data across modules to uncover root causes of yield variation. Scope includes evaluation of bevel and wafer edge behaviour, assessment of process sensitivity, and development of improved inspection algorithms to better represent true edge exclusion performance.

Learning Opportunities:
The intern will gain hands‑on exposure to semiconductor process integration, yield analysis methodologies, statistical data analysis, and defect inspection systems. The role develops problem‑solving skills, engineering judgement, and experience working with multi-functional engineering team members.

Deliverable:
Key deliverables include closure of an estimated N and W yield gap of approximately 0.9%, advancement of wafer edge exclusion targets towards zero non‑live dies at a defined edge exclusion width, and the development of an improved wafer inspection algorithm that excludes known non‑process detractors while accurately reflecting edge performance.

Impact of Project:
The project contributes directly to improved yield stability, enhanced inspection accuracy, and stronger manufacturing decision‑making based on robust data insights.

Skillsets Required:
Analytical thinking, semiconductor process knowledge, statistical data analysis capability, defectivity interpretation skills, and the ability to translate data findings into engineering insights.

Course of Interest:
Microelectronics, Electrical Engineering, Chemical Engineering, Materials Science, Semiconductor Physics, or related engineering disciplines.

Duration Period:
Minimum a semester-long, full-time internship of at least 5 months.